1. Field of the Invention
The present invention relates generally to the field of semiconductor packaging, and more particularly to a Package-on-Package (PoP) assembly and a method for manufacturing the same.
2. Description of the Prior Art
With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. To reduce the dimensions of such components, the structures by which these components are packages and assembled with circuit boards must become more compact. In order to meet the requirements of smaller footprints with higher densities, 3D stacking packaging such as PoP (Package-on-Package) assembly has been developed.
A PoP assembly typically includes a top package with a device die bonded to a bottom package with another device die. In PoP designs, the top package may be interconnected to the bottom package through peripheral solder balls. However, the prior art PoP assembly is not able to provide very tight pitch stacking. Further, the prior art PoP assembly has large package form factor and poor warpage control.
In wafer level packaging, the wafer and the dies mounted on the wafer are typically covered with a relatively thick layer of the molding compound. The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging. It is known that wafer warpage continues to be a concern. Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer. Warpage issue is serious especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process that requires fine-pitch RDL process.